The present invention relates generally to integrated circuit assembly testing, and more particularly to a testability interposer for testing sockets and connectors on printed circuit boards.
Integrated circuit assemblies are ubiquitous in modern electronic devices, and a large portion of the industrial sector is devoted to the design and manufacture of such devices. As electronic devices are continually being improved and becoming more sophisticated, so are consumers' expectations for the level of quality of these products. Accordingly, new and improved testing techniques are continuously being sought by manufacturers to test the quality of integrated circuits, printed circuit boards, and integrated circuit assemblies after manufacture and prior to shipment of these devices. While testing entails checking many aspects of the product, such as functionality testing and burn-in testing, one of the most important tests after manufacture is basic continuity testing—that is, testing to ensure that all connections that are supposed to be connected between components of the device (e.g., integrated circuit pins to printed circuit boards, integrated circuit lead wires to pins, traces connections between printed circuit board nodes, etc.) are intact.
One common defect often uncovered during continuity testing is known as an “open” defect. In an open defect, an electrical connection is missing between two points in the circuit where electrical continuity should exist. Open defects typically result from problems in the manufacturing process, such as missing solder due to uneven application of solder paste, the unintentional introduction of particles in the wetting process, etc. Thus, during continuity testing of integrated circuit assemblies, connection defects such as open solder joints are diagnosed.
Detection of open defects is often performed using well-known capacitive lead-frame sensing technologies. For example, U.S. Pat. No. 5,557,209 to Crook et al, U.S. Pat. No. 5,420,500 to Kerschner, and U.S. Pat. No. 5,498,964 to Kerschner et al., all of which are hereby incorporated by reference for all that they teach, describe techniques for detecting opens between integrated circuit signal pins and the mounting substrate (typically a printed circuit board). FIG. 1A shows the basic setup and FIG. 1B shows the equivalent circuit model of capacitive lead-frame testing for open signal pins on an integrated circuit.
As shown, an integrated circuit (IC) die 18 is packaged in an IC package 12. The package 12 includes a lead frame 14 supporting a plurality of pins 10a, 10b. Pads of the IC die 18 are connected to the package pins 10a, 10b at the lead frame 14 via bond wires 16a, 16b. The pins 10a, 10b are supposed to be conductively attached, for example by way of solder joints, to pads 8a, 8b of a printed circuit board (PCB) 6. The test setup shown in FIG. 1A determines whether package pins are properly connected to the PCB 6 at the solder joints. The test setup includes an alternating current (AC) source 2 that applies an AC signal, through a test probe 4a, to a node connected to the pad 8a on the PCB 6 to which a pin under test 10a should be electrically connected. In a typical test environment, the AC signal is typically 8192 Hz at 0.2 volts. A capacitive sensing probe 20 comprising a conductive sense plate 22 and amplifying buffer 24 is placed on top of the integrated circuit package 12. The capacitive sensing probe 20 is connected to a current measuring device 26, such as an ammeter. Another pin 10b of the integrated circuit 12 is connected to a circuit ground via a grounded probe 4b. 
When the test is performed, the AC signal applied to pad 8a appears on the pin 10a of the integrated circuit package 12. Through capacitive coupling, in particular a capacitance Csense formed between the lead frame 14 and sense plate 22, a current Is is passed to the sense plate 22 and then through the amplifying buffer 24 to the current measuring device 26. If the measured current Is falls between predetermined limits, then the pin 10a is properly connected to the pad 8a. If the pin 10a is not connected to the pad 8a, a capacitance Copen is formed between the pad 8a and pin 10a, altering the current Is measured by the current measuring device 26 such that the measured current Is falls outside the predetermined limits, thereby indicating that an open defect is present at the pin connection.
Capacitive probe testing has not traditionally been used to test fixed pins or tied pins because of the lack of diagnostic separability and presence of significant capacitance due to board-mounted bypass capacitors. A fixed pin is usually considered to be a power or ground pin because it cannot be moved easily with a test stimulus. A tied pin is considered to be any pin for which several other pins on the same device (such as an integrated circuit or connector) share the same node. Note that because devices such as integrated circuits and connectors typically provide multiple power and ground pins, the power and ground fixed pins may also be tied pins as well. For purposes of this patent, the terms “fixed” and “tied” will be used interchangeably because the differences in terms of the present invention are slight.
Recent patent applications U.S. patent application Ser. No. 10/703,944, entitled “Methods and Apparatus For Testing And Diagnosing Open Connections For Sockets And Connectors On Printed Circuit Boards” to Parker et al, and U.S. patent application Ser. No. 10/836,862, entitled “Methods and Apparatus For Non-Contact Testing And Diagnosing Open Connections For Connectors On Printed Circuit Boards” to Parker et al., each of which is incorporated by reference for all that it teaches, collectively describe a method for testing opens on fixed and/or tied pins on connectors and sockets by analyzing inherent capacitive structures present in the network. The '944 application extends the capacitive leadframe testing concept to allow the testing of sockets and connectors, especially when they contain large numbers of pins that are connected to ground and power planes, by introducing the concept of engineering capacitances on an appliance that is inserted into a socket to be tested. This appliance with the engineered capacitance structure contains a common node that is ohmically connected to the active signal buffer, which in turn is ohmically contacted by probes that are coupled to tester circuitry. The ability to test fixed nodes depends on the layout and whether the fixed node is adjacent to an accessible signal node.
In particular, this technology creates a “Matched Capacitor Array” (“MCA”) device 30, shown in FIG. 2A, that fits into a socket connector 40 to be tested. The MCA device 30 includes a plurality of pins 31a-31l that contact corresponding respective sockets 41a-41l of the connector 40. The sockets 41a-41l are supposed to be connected to pads 51a-51l of a PCB via joints 52a-52l, represented also as balls A-L, and it is typically the integrity of these joints 52a-52l that is being tested. Each pin 31a-31l has a tiny, engineered capacitance (C) 33a-33l to a common sense plate 34 (surrounded by a Faraday shield 35) that is then fed to a current measuring device 54 (FIG. 2B). The signal pins 33a, 32c, 32e, 32g, 32i, 32k are paired by an engineered pairing capacitance 32a, 32b, 32c, 32d, 32e, 32f to a neighboring power or ground pin 33b, 32d, 32f, 32h, 32j, 32l as shown in FIG. 2A.
The equivalent circuit for this configuration is shown for a capacitively coupled pair of pins 31a and 31b in FIG. 2B. In the illustrative example, the pair-coupling capacitance 32a has been set to 10*C. An AC source generator 52 applies an AC signal to the node 51a on the board to which the socket 41a should be connected. Current transferred to the common sense plate 34 of the MCA 30 is sensed by capacitive sensing probe 36 (FIG. 2A), which grounds the shield 35 via ground channel 37a, 37b. Sensed current on the common sense plate 34 is transferred to the current measuring device 54 over signal channel 38a, 38b. The input to the current measuring device 54 is a virtual ground. The sensed current is proportional to capacitance.
When no opens are present, the signal from signal generator 52 enters joint 52a (ball A). (Note the source impedance is small.) A voltage is developed at joint 52a (ball A). Joint 52b (ball B) is grounded, so the potential across joint 52b (ball B) is zero volts. Thus no current can flow from joint 52b (ball B) to the current meter 54. The value of capacitance measured is C.
If only joint 52a (ball A) is open, no signal will make it to the current meter 54, so the value measured is zero volts.
If only joint 52b (ball B) is open, the grounding of joint 52b (ball B) is prevented. Because the pair-coupling capacitor is much larger (10×) than C, the effective capacitive coupling to the current meter 54 is almost equal to C, resulting in an effective capacitance at the meter of approximately 2*C.
If both joints 52a and 52b (balls A and B) are open, the open on joint 52a (ball A) dominates the result, for a measurement of zero volts. TABLE 1 summarizes the measurement results:
TABLE 1DefectMeasured capacitanceNoneCBall A open0Ball B open2 * CBall A and B open0
In this example, the capacitance measurements are differentiated by at least a value of C. As long as the current meter 54 is sensitive over a range of 0 to 2*C, open defects are detectable and can be diagnosed.
U.S. patent application Ser. No. 10/836,862 evolves this idea by recognizing that the traditional capacitive lead-frame sense plate along with the inherent capacitances of the socket device under test are sufficient to obtain the same diagnostic coverage of the pins without having to insert an appliance into the socket. The technique of '862 describes testing the socket fixed pins implicitly by analyzing inherent capacitive structures (i.e., nearby pins) present in the network.
The above concepts have been extended not only to include fixed open pins but also to inaccessible shorted or open pins in U.S. patent application Ser. No. 11/170,365, entitled “Methods And Apparatus For Non-Contact Testing And Diagnosing Of Open Connections On Non-Probed Nodes” to Parker et al., and in U.S. patent application Ser. No. 10/979,590, entitled “Methods And Apparatus For Non-Contact Testing And Diagnosing Of Inaccessible Shorted Connections”to Parker, both of which are herein incorporated by reference for all that they teach. Inaccessible pins are considered to be nodes for which the tester either does not have probe access to or are purposely selected for non-probing, and therefore cannot be stimulated with an AC source by the tester.
U.S. patent application Ser. No. 10/834,449, entitled “Test Structure Embedded In A Shipping And Handling Cover For Integrated Circuit Sockets And Method For Testing Integrated Circuit Sockets And Circuit Assemblies Utilizing Same” to Parker leverages these ideas for the case where the socket includes a lid or clamping structure that prevents the sense plate from coupling to the pins in the socket. Such sockets are typically mounted on PCBs and used to allow a mating integrated circuit to be added or replaced after the board is manufactured. An exemplary IC mounted to a board via a socket connector is illustrated in FIG. 3, in which an IC 60 is secured in a socket base 70 by means of a lid or clamp plate 72 and a clamp or lock 76. The IC 60 is clamped or locked into place within the socket 70 by a clamp plate 72, which depresses the IC 60 onto a field of contact pin spring fingers 78 that map one-to-one to solder balls (or pins) 66 on the bottom of the socket 70. The IC 60 may make electrical contact with a board 68 via hundreds or thousands of delicate pin spring fingers 78, which map to an array of pads, pins, solder balls or solder columns 66 that are attached to traces, pads or other contact points on the board 68.
As seen in the cross-sectional side view of FIG. 4A and top view of FIG. 4B, which shows an empty, unlocked IC socket 70, the socket lid or clamp plate 72 may have a window or access hole 75 to permit a detachable heat sink 62 (FIG. 3) to be attached to the IC 60 after it is secured within the socket base 70. The heat sink 62 may be connected to the IC 60 through the access hole 75 in the clamp plate 72. If an installed IC 60 must later be removed, the heat sink 62 is removed first to enable movement of the clamp plate 72. The clamp plate 72 may be hinged on one side with a hinge 74 and clamped on one or more sides with one or more clamps 76 or it may be clamped on two or more sides.
FIG. 5A illustrates a socket cover described in U.S. patent application Ser. No. 10/834,449, and FIGS. 5B and 5C illustrate the socket cover of FIG. 5A positioned in the socket of FIGS. 4A and 4B. In particular, a conductive plane 84 is embedded into a shipping and handling cover 80 for a socket 70 of a circuit assembly to facilitate capacitive sense testing of the socket connections. The conductive plane 84 of the shipping and handling cover 80 allows capacitive sense testing of socket pin connections 66 that would otherwise be testable using the techniques of the above-mentioned U.S. patent application. The shipping and handling cover 80 may also include a handle 82 for facilitating insertion and removal of the cover 80 and minimizing damage to the socket contacts.
It has been established that fixed and inaccessible pins on sockets can be tested whenever the pin layout is advantageous, meaning that some amount of coupling exists between an accessible signal pin and the fixed or inaccessible pin that is to be tested. There are some pin layouts, however, that have regions of nodes (e.g., pins) without any coupling capacitance (or at least, in terms of a capacitive sense test to be performed, sufficient amounts of coupling capacitance) to nearby signal nodes. This results in loss of coverage for the existing solutions that are based on capacitive sensing.
Industry has tried to regain some of this coverage through the use of silicon chip based technologies that are inserted into the socket and may include active components such as field effect transistors (FETs). A big drawback of a solution with active components is the need to provide power to the test and thus for the printed circuit board (PCB). Powering the PCB for the socket test requires tri-stating of all other active PCB components that are connected to the socket. Another drawback is the time and cost associated with doing the design and masks for the test chip. Much of these costs are then repeated whenever the pin functionality of the socket changes.
Accordingly, a need exists for a less costly testing solution for detecting open connections on nodes of sockets and connectors regardless of the pin layout.